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INTEGRATED CIRCUITS
DATA SHEET
SAA4956TJ 2.9-Mbit field memory with noise reduction
Preliminary specification File under Integrated Circuits, IC02 1998 Dec 08
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
CONTENTS 1 2 3 4 5 6 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.3 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Field memory function Write operation Read operation Power-up and initialization Old and new data access Memory arbitration logic and self-refresh Cascade operation Test mode operation Noise reduction function Reformatting and formatting Band-splitting Motion detection K-factor Noise shape I2C-bus interface 8 9 10 11 12 13 13.1 13.2 13.3 13.4 13.5 14 15 16 LIMITING VALUES
SAA4956TJ
THERMAL CHARACTERISTICS CHARACTERISTICS APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1998 Dec 08
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Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
1 FEATURES
SAA4956TJ
* 2949264-bit field memory with optional field based noise reduction * 245772 x 12-bit organization * 3.3 V power supply * Inputs fully TTL compatible when using an extra 5 V power supply * High speed read and write operations * FIFO operations: - Full word continuous read and write - Independent read and write pointers (asynchronous read and write access) - Resettable read and write pointers. * Optional field based noise reduction activated by an enable pin and controlled via the I2C-bus * Optional random access by block function (40 words per block) enabled during pointer reset operation * Quasi static (internal self-refresh and clocking pauses of infinite length) * Write mask function * Cascade operation possible * Compatible with SAA4955TJ * 16-Mbit CMOS DRAM process technology * 40-pin SOJ package. 2 GENERAL DESCRIPTION However, the SAA4956TJ has also, in addition to the field memory function, a field based noise reduction circuit. If this function is enabled it can be controlled via the I2C-bus. The maximum storage depth is 245772 words x 12 bits. A FIFO operation with full word continuous read and write could be used as a data delay, for example. A FIFO operation with asynchronous read and write could be used as a data rate multiplier. Here the data is written once, then read as many times as required as long as new data is not written. In addition to the FIFO operations, a random block access mode is accessible during the pointer reset operation. When this mode is enabled, reading and/or writing may begin at, or proceed from, the start address of any of the 6144 blocks. Each block is 40 words in length. Two or more SAA4956TJs can be cascaded to provide a greater storage depth or a longer delay, without the need for additional circuitry. The SAA4956TJ contains separate 12-bit wide serial ports for reading and writing. The ports are controlled and clocked separately, so asynchronous read and write operations are supported. Independent read and write clock rates are possible. Addressing is controlled by read and write address pointers. Before a controlled write operation can begin, the write pointer must be set to zero or to the beginning of a valid address block. Likewise, the read pointer must be set to zero or to the beginning of a valid address block before a controlled read operation can begin.
The SAA4956TJ is a 2949264-bit field memory with an optional field based noise reduction designed for advanced TV applications such as 100/120 Hz TV, PALplus, PIP and 3D comb filter. The SAA4956TJ is functional and pin compatible with the SAA4955TJ. 3 ORDERING INFORMATION TYPE NUMBER SAA4956TJ
PACKAGE NAME SOJ40 DESCRIPTION plastic small outline package; 40 leads (J-bent); body width 10.16 mm VERSION SOT449-1
1998 Dec 08
3
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
4 QUICK REFERENCE DATA SYMBOL Tcy(SWCK) Tcy(SRCK) tACC VDD VDD(O) VDD(P) IDD(tot) PARAMETER SWCK cycle time read cycle time (SRCK) read access time after SRCK supply voltage (pin 19) supply voltage (pin 22) supply voltage (pin 21) total supply current (IDD(tot) = IDD + IDD(O) + IDD(P)) minimum read/write cycle; outputs open CONDITIONS NREN = LOW; see Fig.4 NREN = HIGH; see Fig.4 see Fig.11 see Fig.11 MIN. 26 52 26 - 3.0 3.0 3.0 -
SAA4956TJ
TYP. - - - - 3.3 3.3 3.3 27
MAX. - 150 - 21 3.6 3.6 5.5 70
UNIT ns ns ns ns V V V mA
1998 Dec 08
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Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
5 BLOCK DIAGRAM
SAA4956TJ
D0(V0) handbook, full pagewidth to D11(Y7) 12 14 to 3
IE 18
NREN 40
SCL 1
SDA 20
WE 17
RSTW SWCK 16 15
DATA INPUT AND WRITE MASK BUFFER (x13) 12 + 1 I2C-bus control
I2C-BUS INTERFACE
IE internal
SAA4956TJ
D0 internal IE internal
INPUT BUFFER (x3)
3 SERIAL WRITE/READ2 CONTROLLER
NOISE REDUCTION 12 + 1 12 D-field delay
DATA MUX
mini cache write/read2 control + cache transfer
write control
SERIAL WRITE REGISTER 20-WORD (x13) 20 x (12 + 1) PARALLEL WRITE REGISTER 20-WORD (x13) 20 x (12 + 1) read2 control
load write block address read2 acknowledge
write acknowledge
DATA MUX
D0 internal IE internal
12
12
12 + 1 WRITE ADDRESS COUNTER WRITE REGISTER MINI CACHE 12-WORD (x12) READ2 READ REGISTER REGISTER MEMORY ARRAY 245760-WORD (x12) READ2 ADDRESS COUNTER MEMORY ARBITRATION REFRESH ADDRESS LOGIC COUNTER READ ADDRESS COUNTER 20 x 12 PARALLEL READ2 REGISTER 20-WORD (x12) +3.3 V VDD VDD(P) VDD(O) 19 21 22 12 100 nF GND OGND 2 39 DATA MUX DATA OUTPUT BUFFER (x12) 27 to 38 12 Q0(V0) to Q11(Y7) OE RE RSTR SRCK OE internal INPUT BUFFER (x4) 23 24 25 26
MGR687
20 x 12 PARALLEL READ REGISTER 20-WORD (x12) 20 x 12 SERIAL READ REGISTER 20-WORD (x12)
OE internal
20 x 12 SERIAL READ2 REGISTER 20-WORD (x12)
refresh clock CLOCK OSCILLATOR
12 mini cache read control 3
read control
read acknowledge
load read block address
SERIAL READ CONTROLLER
Pin 21 (VDD(P)) should be connected to the supply voltage of the driving circuit that generates the input voltages. This could be, for instance, 5.0 V instead of 3.3 V. Pins 19 and 22 (VDD and VDD(O)) require a 3.3 V supply.
Fig.1 Block diagram.
1998 Dec 08
5
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
6 PINNING SYMBOL SCL GND D11(Y7) D10(Y6) D9(Y5) D8(Y4) D7(Y3) D6(Y2) D5(Y1) D4(Y0) D3(U1) D2(U0) D1(V1) D0(V0) SWCK RSTW WE IE VDD SDA VDD(P) VDD(O) OE RE RSTR SRCK Q0(V0) Q1(V1) Q2(U0) Q3(U1) Q4(Y0) Q5(Y1) Q6(Y2) Q7(Y3) Q8(Y4) Q9(Y5) Q10(Y6) Q11(Y7) OGND NREN 1998 Dec 08 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O digital input ground digital input digital input digital input digital input digital input digital input digital input digital input digital input digital input digital input digital input digital input digital input digital input digital input supply digital I/O supply supply digital input digital input digital input digital input digital output digital output digital output digital output digital output digital output digital output digital output digital output digital output digital output digital output ground digital input serial clock of I2C-bus general purpose ground data input 11, Y input bit 7 if NREN is HIGH data input 10, Y input bit 6 if NREN is HIGH data input 9, Y input bit 5 if NREN is HIGH data input 8, Y input bit 4 if NREN is HIGH data input 7, Y input bit 3 if NREN is HIGH data input 6, Y input bit 2 if NREN is HIGH data input 5, Y input bit 1 if NREN is HIGH data input 4, Y input bit 0 if NREN is HIGH DESCRIPTION
SAA4956TJ
data input 3, U input bits 1, 3, 5, 7 if NREN is HIGH data input 2, U input bits 0, 2, 4, 6 if NREN is HIGH data input 1, V input bits 1, 3, 5, 7 if NREN is HIGH data input 0, V input bits 0, 2, 4, 6 if NREN is HIGH serial write clock write reset clock write enable input enable 3.3 V general purpose supply voltage serial data of I2C-bus 3.3 to 5.5 V supply voltage for protection circuits 3.3 V supply voltage for output circuits output enable read enable reset read serial read clock data output 0, V output bits 0, 2, 4, 6 if NREN is HIGH data output 1, V output bits 1, 3, 5, 7 if NREN is HIGH data output 2, U output bits 0, 2, 4, 6 if NREN is HIGH data output 3, U output bits 1, 3, 5, 7 if NREN is HIGH data output 4, Y output bit 0 if NREN is HIGH data output 5, Y output bit 1 if NREN is HIGH data output 6, Y output bit 2 if NREN is HIGH data output 7, Y output bit 3 if NREN is HIGH data output 8, Y output bit 4 if NREN is HIGH data output 9, Y output bit 5 if NREN is HIGH data output 10, Y output bit 6 if NREN is HIGH data output 11, Y output bit 7 if NREN is HIGH ground for output circuits noise reduction enable 6
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
SAA4956TJ
handbook, halfpage
SCL GND D11(Y7) D10(Y6) D9(Y5) D8(Y4) D7(Y3) D6(Y2) D5(Y1)
1 2 3 4 5 6 7 8 9
40 NREN 39 OGND 38 Q11(Y7) 37 Q10(Y6) 36 Q9(Y5) 35 Q8(Y4) 34 Q7(Y3) 33 Q6(Y2) 32 Q5(Y1) 31 Q4(Y0)
the read operation frequency. In this case the random block access modes are not supported because a second read operation (READ2) is activated with an identical frequency as used in the write operations. The PAN-IC (SAA4995WP) needs approximately the same write frequency for the noise reduction option as the read frequency (32 MHz). To allow this configuration the self-refresh must be switched off via the I2C-bus interface. 7.1.1 WRITE OPERATION
D4(Y0) 10
D3(U1) 11 SAA4956TJ 30 Q3(U1) D2(U0) 12 D1(V1) 13 D0(V0) 14 SWCK 15 RSTW 16 WE 17 IE 18 VDD 19 SDA 20
MGR688
29 Q2(U0) 28 Q1(V1) 27 Q0(V0) 26 SRCK 25 RSTR 24 RE 23 OE 22 VDD(O) 21 VDD(P)
Write operations are controlled by the SWCK, RSTW, WE and IE signals. A write operation starts with a reset write address pointer (RSTW) operation, followed by a complete cycle of the SWCK clock during which time WE and IE must be held HIGH. Write operations between two successive reset write operations must contain at least 40 SWCK write clock cycles while WE is HIGH. To transfer data temporarily stored in the serial write registers to the memory array, a reset write operation is required after the last write operation.
7.1.1.1
Reset write: RSTW
The first positive transition of SWCK after RSTW goes from LOW-to-HIGH resets the write address pointer to the lowest address (-12 decimal), regardless of the state of WE (see Figs 4 and 5). RSTW set-up (tsu(RSTW)) and hold (th(RSTW)) times are referenced to the rising edge of SWCK (see Fig.4). The reset write operation may also be asynchronously related to the SWCK signal if WE is LOW. RSTW needs to stay LOW for a single SWCK cycle before another reset write operation can take place. If RSTW is HIGH for 1024 SWCK write clock cycles while WE is HIGH, the SAA4956TJ will enter a built-in test mode.
Fig.2 Pin configuration.
7.1.1.2
7 FUNCTIONAL DESCRIPTION The functional description is divided into 3 main sections: * The basic field memory function (see Section 7.1) * The optional noise reduction function (used in case the NREN signal is HIGH; see Section 7.2) * The I2C-bus interface function (which controls the noise reduction circuit; see Section 7.3). 7.1 Field memory function
Random write block access mode
The SAA4956TJ will enter random write block access mode if the following signal sequence is applied to control inputs IE and WE during the first four SWCK write clock cycles after a reset write (see Figs 6 and 7): 1. At the 1st and 2nd positive transitions of SWCK, IE must be LOW and WE must be HIGH 2. At the 3rd and 4th positive transitions of SWCK, IE must be HIGH and WE must be LOW 3. At the 5th positive transition of SWCK, the state of WE determines which input pin is used for the block address. If WE is LOW the Most Significant Bit (MSB) of the block address must be applied to the D0 input pin. If WE is HIGH, the MSB of the block address is applied to pin IE.
The basic field memory function is fully compatible with the SAA4955TJ if the NREN signal is LOW. In this case the noise reduction function is bypassed via a data mux. If the NREN signal is HIGH the basic field memory function can only be executed with a write frequency restricted to half of 1998 Dec 08 7
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
During this time, control signals WE and IE will function as defined for normal operation. The remaining 12 bits of the 13-bit write block address must be applied, in turn, to the selected input pin (D0 or IE) at the following 12 positive transitions of SWCK. The Least Significant Bit (LSB) of the write block address is applied at the 17th positive transition of SWCK. A write latency period of 18 additional SWCK clock cycles is required before write access to the new block address is possible. During this time, data is transferred from the serial write and parallel write registers into the memory array and the write pointer is set to the new block address. Block address values between 0 and 6143 are valid. Values outside this range must be avoided because invalid block addresses can result in abnormal operation or a lock-up condition. Recovery from lock-up requires a standard reset write operation. WE must remain LOW from the 3rd positive transition of SWCK to the 17th write latency SWCK clock cycle if the block address is applied to pin D0. If the block address is applied to pin IE, WE must be HIGH on the 5th positive transition of SWCK, may be HIGH or LOW on the 6th transition, and must be LOW from the 7th transition to the 17th write latency SWCK clock cycle. At the 18th write latency SWCK clock cycle, IE and WE may be switched HIGH to prepare for writing new data at the next positive transition of SWCK. The complete write block access entry sequence is finished after the 18th write latency cycle. The LOW-to-HIGH transition on RSTW required at the beginning of the sequence should not be repeated. Additional LOW-to-HIGH transitions on RSTW would disable write block address mode and reset the write pointer.
SAA4956TJ
The address area reserved for the mini cache, accessible after a standard reset operation, is from decimal -12 to -1. The memory array starts at decimal 0 and ends at 245759. Decimal address 0 is identical to block address 0000H. Because a single block address is defined for every 40 words in the memory array, block address 0001H corresponds to decimal address 40. The highest block address is 17FFH. This block has a decimal start address of 245720 and an end address of 245759. If a read or write reset operation is not performed, the next read or write pointer address after 245759 will be address 0 due to pointer wraparound. It should be noted that reset read and write operations should occur together. If one pointer wraps around while the other is reset, either 12 words will be lost or 12 words of undefined data will be read.
7.1.1.4
Data inputs: D0 to D11 and write clock: SWCK
A positive transition on the SWCK write clock latches the data on inputs D0 to D11, provided WE was HIGH at the previous positive transition of SWCK. The data input set-up (tsu(D)) and hold (th(D)) times are referenced to the positive transition of SWCK (see Fig.5). The latched data will only be written into memory if IE was HIGH at the previous positive transition of SWCK.
7.1.1.5
Write enable: WE
Pin WE is used to enable or disable a data write operation. The WE signal controls data inputs D0 to D11. In addition, the internal write address pointer is incremented if WE is HIGH at the positive transition of the SWCK write clock. WE set-up (tsu(WE)) and hold (th(WE)) times are referenced to the positive edge of SWCK (see Fig.8).
7.1.1.6
Input enable: IE
7.1.1.3
Address organization
Two different types of memory are used in the data address area: a mini cache for the first 12 data words after a reset write or a reset read, and a DRAM cell memory array with a 245760 word capacity. Each word is 12 bits long. The mini cache is needed to store data temporarily after a reset operation since a latency period is required before read or write access to the memory array is possible. Latency periods are needed for read or write operations in random read or write block access modes because data is read from, or written to, the memory array. The data in the mini cache can only be accessed directly after a standard reset operation. It cannot be accessed in random read or write block access modes.
Pin IE is used to enable or disable a data write operation from the D0 to D11 data inputs into memory. The latched data will only be written into memory if the IE and WE signals were HIGH during the previous positive transition of SWCK. A LOW level on IE will prevent the data being written into memory and existing data will not be overwritten (write mask function; see Fig.10). The IE set-up (tsu(IE)) and hold (th(IE)) times are referenced to the positive edge of SWCK (see Fig.9).
1998 Dec 08
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Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
7.1.2 READ OPERATION
SAA4956TJ
Read operations are controlled by the SRCK, RSTR, RE and OE signals. A read operation starts with a reset read address pointer (RSTR) operation, followed by a complete cycle of the SRCK clock during which time RE and OE must be held HIGH. Read operations between two successive reset read operations must contain at least 20 SRCK read clock cycles while RE is HIGH.
The data output pins are not controlled by the OE pin and are forced into high impedance mode from the 3rd to the 17th positive transition of SRCK. OE should be held LOW during the read latency period. RE must remain LOW from the 3rd positive transition of SRCK to the 20th read latency SRCK clock cycle. After the 20th read latency SRCK clock cycle, RE and OE may be switched HIGH to prepare for reading new data from the new address block at the next positive transition of SRCK. The complete read block access entry sequence is finished after the 20th read latency cycle. The LOW-to-HIGH transition on RSTR required at the beginning of the sequence should not be repeated. Additional LOW-to-HIGH transitions on RSTR would disable the read block address mode and reset the read pointer.
7.1.2.1
Reset read: RSTR
The first positive transition of SRCK after RSTR goes from LOW-to-HIGH resets the read address pointer to the lowest address (-12 decimal; see Figs 11 and 12). If RE is LOW, however, the reset read operation to the lowest address will be delayed until the first positive transition of SRCK after RE goes HIGH. RSTR set-up (tsu(RSTR)) and hold (th(RSTR)) times are referenced to the rising edge of SRCK (see Fig.11). The reset read operation may also be asynchronously related to the SRCK signal if RE is LOW. RSTR needs to stay LOW for a single SRCK cycle before another reset write operation can take place.
7.1.2.3
Data outputs: Q0 to Q11 and read clock: SRCK
7.1.2.2
Random read block access mode
The SAA4956TJ will enter random read block access mode if the following signal sequence is applied to control inputs RE and OE during the first four SWCK write clock cycles after a reset read (see Fig.13): 1. At the 1st and 2nd positive transitions of SRCK, OE must be LOW and RE must be HIGH 2. At the 3rd and 4th positive transitions of SRCK, OE must be HIGH and RE must be LOW. During this time, control signals RE and OE will function as defined for normal operation. The Most Significant Bit (MSB) of the block read address is applied to the OE input pin at the 5th positive transition of SRCK. The remaining 12 bits of the 13-bit read block address must be applied, in turn, to OE at the following 12 positive transitions of SWCK. The Least Significant Bit (LSB) of the block address is applied at the 17th positive transition of SRCK. A read latency period of 20 additional SRCK clock cycles is required before read access to the new block address is possible. During this period, data is transferred from the memory array to the serial read and parallel read registers and the read pointer is set to the new block address. Block address values between 0 and 6143 are valid. Values outside this range must be avoided because invalid block addresses can result in abnormal operation or a lock-up condition. Recovery from lock-up requires a standard reset read operation. 1998 Dec 08 9
The new data is shifted out of the data output registers on the rising edge of the SRCK read clock provided RE and OE are HIGH. Data output pins are low impedance if OE is HIGH. If OE is LOW, the data outputs are high impedance and the data output bus may be used by other devices. Data output hold (th(Q)) and access times (tACC) are referenced to the positive transition of SRCK. The output data becomes valid after access time interval tACC (see Fig.12). Data output pins Q0 to Q11 are TTL compatible with the restriction that when the outputs are high impedance, they must not be forced higher than VDD(O) + 0.5 V or 5.0 V absolute. The output data has the same polarity as the incoming data at inputs D0 to D11.
7.1.2.4
Read enable: RE
RE is used to increment the read pointer. Therefore, RE needs to be HIGH at the positive transition of SRCK. When RE is LOW, the read pointer is not incremented. RE set-up (tsu(RE)) and hold times (th(RE)) are referenced to the positive edge of SRCK (see Fig.14).
7.1.2.5
Output enable: OE
OE is used to enable or disable data outputs Q0 to Q11. The data outputs are enabled (low impedance) if OE is HIGH. OE LOW disables the data output pins (high impedance). Incrementing of the read pointer does not depend on the status of OE. OE set-up (tsu(OE)) and hold times (th(OE)) are referenced to the positive edge of SRCK (see Fig.15).
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
7.1.3 POWER-UP AND INITIALIZATION 7.1.5
SAA4956TJ
MEMORY ARBITRATION LOGIC AND SELF-REFRESH
Reliable operation is not guaranteed until at least 100 s after power-up, the time needed to stabilize VDD within the recommended operating range. After the 100 s power-up interval has elapsed, the following initialization sequence must be performed: a minimum of 12 dummy read operations (SRCK cycles) followed by a reset read operation (RSTR), and a minimum of 12 dummy write operations (SWCK) followed by a reset write operation (RSTW). Read and write initialization may be performed simultaneously. If initialization starts earlier than the recommended 100 s after power-up, the initialization sequence described above must be repeated, starting with an additional reset read operation and an additional reset write operation after the 100 s start-up time. 7.1.4 OLD AND NEW DATA ACCESS
Since the data in the memory array is stored in DRAM cells, it needs to be refreshed periodically. Refresh is performed automatically under the control of internal memory arbitration logic which is clocked by a free running clock oscillator. The memory arbitration logic controls memory access for read, write and refresh operations. It uses the contents of the write, read and refresh address counters to access the memory array to load data from the parallel write register, store data in the parallel read register, or to refresh stored data. The values in these counters correspond to block addresses. 7.1.6 CASCADE OPERATION
If a longer delay is needed, the total storage depth can be increased beyond 2949264 bits by cascading several SAA4956TJs. For details see the interconnection and timing diagrams (Figs 18 and 19). The noise reduction function can be realized by enabling this function with the NREN pin at one of the cascaded SAA4956TJs. 7.1.7 TEST MODE OPERATION
A minimum delay of 40 SWCK clock cycles is needed before newly written data can be read back from memory (see Fig.16). If a reset read operation (RSTR) occurs in a read cycle before a reset write operation (RSTW) in a write cycle accessing the same location, then old data will be read. Old data will be read provided a data read cycle begins within 20 pointer positions of the start of a write cycle. This means that if a reset read operation begins within 20 SWCK clock cycles after a reset write operation, the internal buffering of the SAA4956TJ will ensure that old data will be read out (see Fig.17). New data will be read if the read pointer is delayed by 40 pointer positions or more after the write pointer. Old data is still read out if the write pointer is less than or equal to 20 pointer positions ahead of the read pointer (internal buffering). A write pointer to read pointer delay of more than 20 but less than 40 pointer positions should be avoided. In this case, the old or the new data may be read, or a combination of both. In random read and write block access modes, the minimum write-to-read new data delay of 40 SWCK clock cycles must be inserted for each block.
The SAA4956TJ incorporates a test mode not intended for customer use. If WE and RSTW are held HIGH continuously for 1024 SWCK clock cycles, the SAA4956TJ will enter test mode. It will exit test mode if WE is LOW for a single SWCK cycle or if RSTW is LOW for 2 SWCK clock cycles.
1998 Dec 08
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Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
7.2 Noise reduction function
data input D0(V0), D1(V1) D2(U0), D3(U1) 4 I2C-bus control: chroma_inverted DPCMin REFORMATTER new U/V D-field delay D0(V0), D1(V1) D2(U0), D3(U1) 4 REFORMATTER old U/V new Y data input D11(Y7) to D4(Y0) 8
SAA4956TJ
handbook, full pagewidth
D-field delay D11(Y7) to D4(Y0) 8
old Y
+
delta U/V
LOW-PASS FILTER 1 I2C-bus control: unfiltered LF delta U/V I2C-bus control: unfiltered
LOW-PASS FILTER 1
+
-
-
delta Y
-
+
LF delta Y
-
+
ABS/LIMITER
HF delta U/V
HF delta Y
U/V AVERAGE
ABS/LIMITER
LOW-PASS FILTER 2 I2C-bus control: Cadapt_gain
LOW-PASS FILTER 2 I2C-bus control: chromafix and Klumatochroma Kchroma Kchromafix Kluma I2C-bus control: Yadapt_gain
x
x
I2C-bus control: lumafix Klumafix Kluma
x + +
processed U/V LUT
x + +
processed Y
LUT
I2C-bus control: noise_shape
NOISE SHAPE
I2C-bus control: noise_shape
NOISE SHAPE
I2C-bus control: DPCMout
FORMATTER 4 D to memory D0(V0), D1(V1) D2(U0), D3(U1) 8 D to memory D11(Y7) to D4(Y0)
MGR689
Switch position is off.
Fig.3 Block diagram of noise reduction.
1998 Dec 08
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Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
The main function of the noise reduction is shown in Fig.3. It is divided in two signal paths for chrominance and luminance. Two operating modes can be used in principal: the fixed and the adaptive mode. In both modes the applied frequency range, where the noise reduction takes place, can be reduced or not reduced (I2C-bus control: unfiltered). The noise reduction operates field recursive with an average ratio between fresh (new) and over previous fields averaged (old) luminance and chrominance. Noise reduction can be activated by forcing the NREN control signal to HIGH. In this case the system starts with default settings for noise reduction and noise shape, if clock is applied to SWCK. If NREN is LOW the noise reduction block is bridged via a data mux (see Fig.1). During NREN HIGH, only half of the write frequency, which is allowed during NREN LOW, can be applied. This is explained by the need for a second memory read access (READ2) to get old data (D-field delay) in the same frequency as the write frequency. The noise reduction is controlled via I2C-bus settings. Since the PAN-IC (SAA4995WP) needs approximately the same write frequency as the read frequency for the noise reduction option (32 MHz), a deactivated self-refresh is required. This setting can be done via the I2C-bus interface (I2C-bus control: no_refresh). In the fixed mode, the noise reduction produces a constant weighted input averaging. Because of smearing effects this mode should not be used for normal operation except for K = 1. The fixed mode can be activated separately for chrominance (I2C-bus control: chromafix) and luminance (I2C-bus control: lumafix). In the adaptive mode, the averaging ratio (K-factor) is based on the absolute differences of luminance respectively chrominance among the inputs. When the absolute difference is low, only a small part of the fresh data will be added. In cases of high difference, much of fresh data will be taken. This occurs in either situation of movement or where a significant vertical contrast is seen. The relation between the amount of movement and the K-factor values is defined via a Look-Up Table (LUT) where the steps can be programmed (I2C-bus controls: Ksteps). It should be noted that recursion is done over fields, and that pixel positions between the new and old fields always have a vertical offset of one line. So averaging is not only done in the dimension of time but also in the vertical direction. Therefore averaging vertically on e.g. a vertical black to a white edge would provide a grey result.
SAA4956TJ
The averaging in chrominance can be slaved optionally to the luminance averaging (I2C-bus control: Klumatochroma), therefore chrominance differences are not taken into account for the K-factor setting of the chrominance signal path. The noise reduction scheme effectively also decreases the cross-colour patterns if for the averaging in chrominance the adaptive noise reduction is slaved to the luminance averaging (I2C-bus control: Klumatochroma). The cross-colour pattern does not produce an increase of the measured luminance difference, therefore this pattern will be averaged over many fields. 7.2.1 REFORMATTING AND FORMATTING
The standard applications are using the 4 : 1 : 1 YUV data stream (see Table 1). The noise reduction processing uses internally the 4 : 2 : 2 data stream. An up converter to 4 : 2 : 2 is applied with a linear interpolation filter for creation of the extra samples. These are combined with the original samples from the 4 : 1 : 1 stream. Instead of the 4 : 1 : 1 mode the input or output colour can be handled as DPCM format which is a certain data compression (I2C-bus control: DPCMin, DPCMout) if the 4 : 2 : 2 data bandwidth is needed e.g. for applications together with SAA4978H. The incoming colour data can be also inverted for special purposes (I2C-bus control: Chroma_inverted). Table 1 Digital input and output bus format 4 : 1 : 1 FORMAT Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 V07 V06 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 U05 U04 V05 V04 Y27 Y26 Y25 Y24 Y23 Y22 Y21 Y20 U03 U02 V03 V02 Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 U01 U00 V01 V00 INPUT PIN D11(Y7) D10(Y6) D9(Y5) D8(Y4) D7(Y3) D6(Y2) D5(Y1) D4(Y0) D3(U1) D2(U0) D1(V1) D0(V0)
1998 Dec 08
12
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
The start position, when the first phase of the 4 : 1 : 1 YUV data word is expected on the input bus, is defined by the first valid written or read word after a reset write or a reset read operation. The luminance input signal is expected in 8-bit straight binary format, whereas U and V input signals are expected in twos complement format. U and V input signals are inverted if the corresponding I2C-bus control bit chroma_invert is set to logic 1. 7.2.2 BAND-SPLITTING
SAA4956TJ
After reformatting, the frequencies of the difference signals of luminance (delta Y) and chrominance (delta U/V) can be divided optionally in an upper band (HF) and lower band (LF) with a lowpass-filter in both signal paths. The lower frequency band signals (LF delta Y and LF delta U/V) will be used as input for the noise reduction function. The lower frequency band on these signals means that the specific picture contents does not move or is moving slowly. Optionally, it is possible to bridge the band-splitting (I2C-bus control: unfiltered = 1). 7.2.3 MOTION DETECTION
The amplified signals, which correlate to the amount of movement in the chrominance respectively luminance signal path, are transferred into 1 out of 16 possible K-factor values via look-up tables. The K-factor values are defined by step values of the look-up tables. The step values are programmed via the I2C-bus-controls: Kstep0 to Kstep7 (see Table 3). These values are valid for the look-up tables of the chrominance and the luminance. For example, Kstep3 = 4 means: values which are smaller than 8 (4 times weight of 2) are at least K = 38 or smaller and values equal or higher than 8 are at least K = 48 or higher. 7.2.4 K-FACTOR
The same signals, on which the noise reduction will be applied, are used to detect the amount of motion in the difference signals. Therefore, the absolute value of the difference signals are generated and limited to a maximum value. Afterwards the absolute values of the difference signal of U and V are averaged. The signals are low-pass filtered to smooth these signals. The filtered signals are amplified, depending on the setting of the I2C-bus controls: Yadapt_gain respectively Cadapt_gain (see Table 2). Table 2 Gain settings of adaptive values for chrominance and luminance GAIN HEX 00 01 02 03 04 05 06 07 DECIMAL 00 01 02 03 04 05 06 07
1 8 2 8 4 8 8 8 16 8 32 8 64 8 128 8
The amount of noise reduction (field averaging) is described via the K-factor. K = 1 means that no averaging is applied and the new field information is used. K = 0 means that no averaging is applied and thus only the old field information is used like a still picture mode. All values in between mean that a weighted averaging is applied. It is possible to use fixed K-factor values if the I2C-bus variable lumafix respectively chromafix is set to logic 1. The possible fixed K-factor values of the I2C-bus control variables Klumafix and Kchromafix are described in Table 3. Table 3 Settings of fixed K-factor values K-factor HEX 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F DECIMAL 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 0
1 2 3 4 5 6 7 8 9 16 16 16 16 16 16 16 16
Klumafix/Kchromafix[3 to 0]
Yadapt_gain/Cadapt_gain[2 to 0]
16 10 16 11 16 12 16 13 16 14 16 16 16
1998 Dec 08
13
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
7.2.5 NOISE SHAPE
SAA4956TJ
If the noise shaping is activated possible shadow picture information in the chrominance and the luminance path, resulting from a low K-factor value, will be eliminated. The noise shaping function can be switched off by means of the I2C-bus control. Subregister noise_shape = 0 is applied to show the effect. 7.3 I2C-bus interface
There is no `wrap around' of subaddresses. Commands and data are processed as soon as they have been completely received. Data patterns sent to the various subaddresses are not checked for being illegal or not at that address. Detection of a STOP condition without a preceding acknowledge bit is regarded as a bus error. The last operation will not then be executed. Invalid subaddresses are not acknowledged. The default I2C-bus settings can be loaded by changing the state of the NREN pin from LOW to HIGH during clocking of the SWCK and SCL pins. This can be realized for example by delaying the NREN signal with an RC-circuit for 1 second during the power-up sequence. This is necessary to give the circuit a minimum of 20 cycles of SCL and 100 cycles of SWCK after all input signals are stabilized.
The I2C-bus interface in the SAA4956TJ is used in a receive mode. The standardized bus frequencies of both 100 kHz and 400 kHz can be dealt with. As a slave receiver, the SAA4956TJ provides 8 registers for storing commands and data. These registers are accessed via so-called subaddresses. A subaddress can be thought of as a pointer to an internal memory location. It is allowed to send one data byte or more data bytes per transmission to the SAA4956TJ. In this event, the subaddress is automatically incremented after each data byte, resulting in storing the sequence of data bytes at successive register locations, starting at SUBADDRESS. A transmission can start at any valid subaddress. Each data byte is acknowledged with ACK (acknowledge). Table 4 S
I2C-bus control; slave address, subaddress and data format 0 ACK SUBADDRESS ACK DATA ACK ... DATA ACK P
SLAVE ADDRESS
Table 5
Description of bits used in Table 4 BIT FUNCTION START condition 7-bit device address: 1011 111 (last bit is LSB) data direction bit (write to device) acknowledge address of register to write to data byte to be written into register STOP condition
S SLAVE ADDRESS 0 ACK SUBADDRESS DATA P
1998 Dec 08
14
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
Table 6 Write registers BIT NAME DEFAULT FUNCTION
SAA4956TJ
REGISTER
Subregister 20H to 23H (Ksteps of the look-up tables of luminance and chrominance) 20H 21H 22H 23H 0 to 3 Kstep0 4 to 7 Kstep1 0 to 3 Kstep2 4 to 7 Kstep3 0 to 3 Kstep4 4 to 7 Kstep5 0 to 3 Kstep6 4 to 7 Kstep7 2 3 4 6 4 6 4 6 step in adaptive curve from K = 116 to K = 18; weight of 1 step in adaptive curve from K = 18 to K = 28; weight of 1 step in adaptive curve from K = 28 to K = 38; weight of 2 step in adaptive curve from K = 38 to K = 48; weight of 2 step in adaptive curve from K = 48 to K = 58; weight of 4 step in adaptive curve from K = 58 to K = 68; weight of 4 step in adaptive curve from K = 68 to K = 78; weight of 8 step in adaptive curve from K = 78 to K = 88; weight of 8 value of the fixed K-factor of the luminance; see Table 3 value of the gain of the adaptive curve of the luminance; see Table 2 adaptive (lumafix = 0) or fixed K mode (lumafix = 1) of the luminance
Subregister 24H (K-factor controls of luminance) 24H 0 to 3 Klumafix 4 to 6 Yadapt_gain 7 lumafix 15 1 0
Subregister 25H (K-factor controls of chrominance) 25H 0 to 3 Kchromafix 4 to 6 Cadapt_gain 7 chromafix 15 1 0 value of the fixed K-factor of the luminance; see Table 3 value of the gain of the adaptive curve of the chrominance; see Table 2 adaptive (chromafix = 0) or fixed K mode (chromafix = 1) of chrominance
Subregister 26H (miscellaneous) 26H 0 1 2 3 4 5 6 7 DPCMin DPCMout 0 0 if HIGH: converts the chrominance input from DPCM to 4 : 2 : 2 format if HIGH: converts the chrominance output from 4 : 2 : 2 to DPCM format if HIGH: uses luminance K-factor for chrominance path if HIGH: band splitting is deactivated, complete difference signals are used if HIGH: noise shaping is activated if HIGH: chrominance input signals U and V are inverted if HIGH: demo mode is activated with noise reduction only at the right screen side
Klumatochroma 0 unfiltered noise_shape chroma_invert split_screen reserved 0 1 0 0
Subregister 27H (miscellaneous) 27H 0 1 no_refresh field_sync 0 0 if HIGH: disables internal self-refresh to allow Tcy(SWCK) = 29 ns for PAN-IC if HIGH: synchronizes the noise reduction via RSTW (split_screen and DPCM not possible). Otherwise sync is line related detected by WE 5 cycle LOW followed by a HIGH cycle.
2 to 7 reserved 1998 Dec 08 15
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VDD(O) VDD(P) VI VO IDD(tot) PARAMETER supply voltage (pin 19) supply voltage (pin 22) supply voltage for protection circuits input voltage output voltage total supply current VDD(P) = 5 V VDD(P) = 5 V CONDITIONS MIN. -0.5 -0.5 -0.5 -0.5 -0.5 - -0.5 - - -20 0 0 note 1 note 2 Notes -200 -2000 VDD = VDD(O) = VDD(P) = 3.3 V -0.5 VDD = VDD(O) = VDD(P) = 3.3 V -0.5 VGND-OGND voltage difference between GND and OGND IO(sc) Ptot Tstg Tj Tamb Ves short-circuit output current total power dissipation storage temperature junction temperature ambient temperature electrostatic handling
SAA4956TJ
MAX. +5 +5 +5.5 +5.5 +3.8 +5 +3.8 200 +0.5 50 750 +150 125 70 +200 +2000 V V V V V V V
UNIT
mA V mA mW C C C V V
1. Machine model: equivalent to discharging a 200 pF capacitor through a 0 series resistor (`0 ' is actually 0.75 H + 10 ). 2. Human body model: equivalent to discharging a 100 pF capacitor through a 1500 series resistor. 9 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 60 UNIT K/W
1998 Dec 08
16
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
SAA4956TJ
10 CHARACTERISTICS VDD = VDD(O) = VDD(P) = 3.0 to 3.6 V; Tamb = 0 to 70 C; 3 ns input transition times; unless otherwise specified. SYMBOL Supply VDD VDD(O) VDD(P) IDD(tot) supply voltage (pin 19) supply voltage (pin 22) supply voltage (pin 21) total supply current (IDD(tot) = IDD + IDD(O) + IDD(P)) operating supply current stand-by supply current minimum write/read cycle; outputs open-circuit after 1 RSTW/RSTR cycle; NREN, WE, RE and OE = LOW minimum write/read cycle; outputs open-circuit 3.0 3.0 3.0 - 3.3 3.3 3.3 27 3.6 3.6 5.5 70 V V V mA PARAMETER CONDITIONS MIN. TYP.(1) MAX. UNIT
IDD IDD(std)
minimum write/read cycle - -
25 3
60 10
mA mA
IDD(O)
supply current
-
2
10
mA
IDD(P)
supply current
-
0 - - - - - - - - - - - - - - - - - - -
1
mA
Inputs except I2C-bus signals (pins 3 to 18, 23 to 26 and 40) VIH VIL ILI Ci HIGH-level input voltage LOW-level input voltage input leakage current input capacitance Vi = 0 V to VDD(P) f = 1 MHz; Vi = 0 V 2.0 -0.5 -10 - VDD(P) + 0.3 V +0.8 +10 7 V A pF
Inputs of I2C-bus signals: SCL (pin 1) and SDA (pin 20); note 2 VIH VIL ILI Ci HIGH-level input voltage LOW-level input voltage input leakage current input capacitance Vi = 0 V to VDD(P) f = 1 MHz; Vi = 0 V IOH = -5 mA IOL = 4.2 mA f = 1 MHz; Vo = 0 V 3.0 -0.5 -10 - VDD(P) + 0.5 V +1.5 +10 10 - 0.4 +10 10 V A pF
Outputs except I2C-bus signal SCL (pins 27 to 38) VOH VOL ILO Co HIGH-level output voltage LOW-level output voltage output leakage current output capacitance 2.4 - -10 - - -10 f = 1 MHz; Vo = 0 V NREN = LOW; see Fig.4 NREN = HIGH; see Fig.4 tW(SWCKH) tW(SWCKL) 1998 Dec 08 SWCK HIGH pulse width SWCK LOW pulse width see Fig.4 see Fig.4 17 - V V A pF
Output of I2C-bus signal: SDA (pin 20); note 2 VOL ILO Co Tcy(SWCK) LOW-level output voltage output leakage current output capacitance IOL = 4 mA 0.4 +10 10 - 150 - - V A pF
Write cycle timing; note 3 SWCK cycle time 26 52 7 7 ns ns ns ns
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
SAA4956TJ
SYMBOL tsu(D) th(D) tsu(RSTW) th(RSTW) tsu(WE) th(WE) tW(WEL) tsu(IE) th(IE) tW(IEL) tt tACC ten(Q) tdis(Q) th(Q) Tcy(SRCK) tW(SRCKH) tW(SRCKL) tsu(RSTR) th(RSTR) tsu(RE) th(RE) tW(REL) tsu(OE) th(OE) tW(OEL) tt Notes
PARAMETER hold time data inputs (D0 to D11) set-up time RSTW hold time RSTW set-up time WE hold time WE WE LOW pulse width set-up time IE hold time IE IE LOW pulse width transition time (rise and fall)
CONDITIONS see Fig.4 see Fig.4 see Fig.4 see Fig.8 see Fig.8 see Fig.8 see Fig.9 see Fig.9 see Fig.9 see Fig.4
MIN. 5 3 5 3 5 3 8 5 3 8 - - - - 3 26 7 7 5 3 5 3 9 5 3 9 -
TYP.(1) - - - - - - - - - - 3 - - - - - - - - - - - - - - - 3 - - - - - - - - - - 30
MAX.
UNIT ns ns ns ns ns ns ns ns ns ns ns
set-up time data inputs (D0 to D11) see Fig.4
Read cycle timing; note 4 access time after SRCK output enable time after SRCK output disable time after SRCK output hold time after SRCK SRCK cycle time HIGH-level pulse width of SRCK LOW-level pulse width of SRCK set-up time RSTR hold time RSTR set-up time RE hold time RE LOW-level pulse width of RE set-up time OE hold time OE LOW-level pulse width of OE transition time (rise and fall) see Fig.11 see Fig.15 note 5; see Fig.15 see Fig.11 see Fig.11 see Fig.11 see Fig.11 see Fig.11 see Fig.11 see Fig.14 see Fig.14 see Fig.14 see Fig.15 see Fig.15 see Fig.15 see Fig.11 21 21 12 - - - - - - - - - - - - 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1. Typical values are valid for Tamb = 25 C, VDD = VDD(O) = VDD(P) = 3.3 V, all voltages referenced to GND. See Fig.1 for configuration. 2. The AC characteristics are in accordance with the I2C-bus specification for fast mode (clock frequency maximum 400 kHz). Information about the I2C-bus can be found in the brochure "The I2C-bus and how to use it" (order number 9398 393 40011). 3. The write cycle timing set-up and hold times are related to VIL of the rising edge of SWCK. They are valid for the specified LOW and HIGH-level input voltages (VIL and VIH). 4. The read cycle timing set-up and hold times are related to VIL of the rising edge of SRCK. They are valid for the specified LOW and HIGH-level input voltages (VIL and VIH). The load on each output is a 30 pF capacitor to ground in parallel with a 218 resistor to 1.31 V. 5. Disable times specified are from the initiating edge until the output is no longer driven by the memory. Disable times are measured by observing the output waveforms. Low values of load resistor and capacitor have to be used to obtain a short time constant. 1998 Dec 08 18
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
SAA4956TJ
N handbook, full pagewidth - 2 Tcy(SWCK) SWCK
N-1
N
1
2 -VIH -VIL
th(RSTW) tw(SWCKH) tw(SWCKL) th(RSTW) RSTW tsu(D) tsu(RSTW)
tt tsu(RSTW) -VIH -VIL
th(D) D0 to D11 N-2 N-1 N 1 2 -VIH -VIL -VIH -VIL -VIH -VIL
MGK677
WE
IE
Fig.4 Write cycle timing diagram (reset write).
handbook, full pagewidth - 1 N
N Tcy(SWCK)
disable
disable
1 -VIH -VIL
SWCK
tw(SWCKH) RSTW
tw(SWCKL)
-VIH -VIL
D0 to D11
N-1
N
1
-VIH -VIL -VIH -VIL -VIH -VIL
WE
IE
MGK678
Fig.5 Write cycle timing diagram (reset write with WE LOW).
1998 Dec 08
19
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
SAA4956TJ
handbook, full pagewidth
start sequence (4 SWCK) 2 3 4 5
serial input of write block address (13 SWCK) 17
write latency (minimum 18 SWCK) 18 19 34 35 36
write data
1 SWCK
RSTW WE LOW: D0 controlled WE
IE
random write block address D0
MSB LSB
write data 0 at block address: write data 1 2 3
D1 to D11
0
1
2
3
MGK679
Fig.6 D0 controlled entry sequence of the random write block access mode.
handbook, full pagewidth
start sequence (4 SWCK) 2 3 4 5
serial input of write block address (13 SWCK) 17
write latency (minimum 18 SWCK) 18 19 34 35 36
write data
1 SWCK
RSTW WE HIGH: IE controlled
WE
random write block address IE
MSB LSB
at block address: write data D0 to D11 0 1 2 3
MGK680
Fig.7 IE controlled entry sequence of the random write block access mode.
1998 Dec 08
20
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
SAA4956TJ
N handbook, full pagewidth - 1 SWCK
N
disable
disable
N+1 -VIH -VIL
tsu(WE)
th(WE) tsu(WE)
th(WE)
WE tw(WEL) tsu(D) N-1 th(D) N N+1
-VIH -VIL
D0 to D11
-VIH -VIL -VIH -VIL -VIH -VIL
IE
RSTW
MGK681
Fig.8 Write cycle timing diagram (write enable).
N handbook, full pagewidth- 1 SWCK
N
disable
disable
N+3 -VIH -VIL
tsu(IE)
th(IE) tsu(IE)
th(IE)
IE tw(IEL) tsu(D) N-1 th(D) N N+3
-VIH -VIL
D0 to D11
-VIH -VIL -VIH -VIL -VIH -VIL
WE
RSTW
MGK682
Fig.9 Write cycle timing diagram (input enable = write mask operation).
1998 Dec 08
21
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
SAA4956TJ
handbook, full pagewidth
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7 -VIH -VIL
SWCK
IE
-VIH -VIL
WE
-VIH -VIL
D0 to D11
N
N+1
N+2
N+3
N+6
N+7
-VIH N+8 -VIL
RSTW
-VIH -VIL N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 -VIH -VIL
SRCK
OE
-VIH -VIL
RE
-VIH -VIL new new high-Z N N+3 old N+4 old N+5 new N+6 new N+7 new N+8 -VIH -VIL
Q0 to Q11
RSTR
MGK683
-VIH -VIL
Fig.10 Write mask operation.
1998 Dec 08
22
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
SAA4956TJ
N handbook, full pagewidth- 1 Tcy(SRCK) SRCK
N
1
2
3 -VIH -VIL
tw(SRCKH) tw(SRCKL) RSTR th(RSTR)
th(RSTR) tsu(RSTR)
tt tsu(RSTR) -VIH -VIL
tACC Q0 to Q11 N-2
th(Q) N-1 N 1 2 -VIH -VIL -VIH -VIL -VIH -VIL
MGK684
RE
OE
Fig.11 Read cycle timing diagram (reset read).
handbook, full pagewidthN
N Tcy(SRCK)
N
1
2 -VIH -VIL
SRCK
tw(SRCKH) tw(SRCKL) RSTR -VIH -VIL tACC Q0 to Q11 N-1 N tACC 1 -VIH -VIL -VIH -VIL -VIH -VIL
MGK685
RE
OE
Fig.12 Read cycle timing diagram (reset read with RE LOW).
1998 Dec 08
23
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
SAA4956TJ
handbook, full pagewidth
start sequence (4 SRCK) 2 3 4 5
serial input of read block address (13 SRCK) 17
read latency (minimum 20 SRCK) 18 19 36 37 38
read data
1 SRCK
RSTR
RE
random read block address OE
MSB LSB
at block address: read data Q0 to Q11 high-Z 0 1 2
MGK686
Fig.13 Entry sequence of the random read block access mode.
handbook, full pagewidthN
N
N
N+1
N+2 -VIH -VIL
SRCK
tsu(RE)
th(RE) tsu(RE)
th(RE)
RE tw(REL) Q0 to Q11 N-1 N
-VIH -VIL tACC N+1 -VIH -VIL -VIH -VIL -VIH -VIL
MGK687
OE
RSTR
Fig.14 Read cycle timing diagram (read enable).
1998 Dec 08
24
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
SAA4956TJ
handbook, full pagewidth N
disable
disable
N+3
N+4 -VIH -VIL
SRCK
tsu(OE)
th(OE) tsu(OE)
th(OE)
OE tw(OEL) tdis(Q) N-1 high-Z N
-VIH -VIL tACC ten(Q) N+3 -VIH -VIL -VIH -VIL -VIH -VIL
MGK688
Q0 to Q11
RE
RSTR
Fig.15 Read cycle timing diagram (output enable).
1998 Dec 08
25
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
SAA4956TJ
handbook, full pagewidth
1
2
3
39
40
41
42 -VIH -VIL
SWCK
RSTW
-VIH -VIL
WE and IE
-VIH -VIL new new 2 new 3 new 39 new 40 new 41 new 42 -VIH -VIL
D0 to D11
1
minimum number of SWCK cycles delay to get new data 1 2 3 -VIH -VIL
SRCK
RSTR
-VIH -VIL
RE and OE
-VIH -VIL new new 2
MGK689
Q1 to Q11
high-Z 1
-VIH -VIL
Fig.16 New data access.
1998 Dec 08
26
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
SAA4956TJ
handbook, full pagewidth
1
2
3
19
20
21
22 -VIH -VIL
SWCK
RSTW
-VIH -VIL
WE and IE
-VIH -VIL new new 2 new 3 new 19 new 20 new 21 new 22 -VIH -VIL
D0 to D11
1
maximum number of SWCK cycles delay to get old data 1 2 3 -VIH -VIL
SRCK
RSTR
-VIH -VIL
RE and OE
-VIH -VIL old old 2
MGK690
Q1 to Q11
high-Z 1
-VIH -VIL
Fig.17 Old data access.
1998 Dec 08
27
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
SAA4956TJ
reset handbook, full pagewidth signal serial clock RSTR SRCK Q0(V0) to Q11(Y7) 12 WE IE 17 18 24 23 RE OE WE IE 17 18 24 23 RE OE RSTW SWCK D0(V0) to D11(Y7) RSTR SRCK Q0(V0) to Q11(Y7) 12
RSTW SWCK D0(V0) to D11(Y7) 12
16 15
25 26
16 15
25 26
SAA4956TJ
14 to 3 27 to 38
SAA4956TJ
14 to 3 27 to 38
data inputs
data outputs
enable signal
MGR690
Fig.18 Cascade operation (signal connections).
handbook, full pagewidth
write new data read 2 times delayed old data
1
1 2
2 3
3 4
4 5
5 6
6 7 -VIH -VIL
SWCK and SRCK
RSTW and RSTR
-VIH -VIL
WE and IE and RE and OE
-VIH -VIL new new 2 new 3 new 4 new 5 new 6 -VIH -VIL
data inputs (x12)
1
old data outputs (x12) high-Z 1
old 2
old 3
old 4
old 5
old 6
MGK692
-VIH -VIL
Fig.19 Cascade operation (timing waveforms).
1998 Dec 08
28
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
11 APPLICATION INFORMATION
SAA4956TJ
handbook, full pagewidth
+3.3 V 8, 11, 69, 75, 80
+5 V 17, 18, 19, 23, 25, 29, RST 46, 67 9
YIN UIN VIN +3.3 V 19, 22 1 3 4 5 6 7 8 9 10 11 12 13 14 20 25 10 k NREN 4.7 F 26 40 2, 39 +5 V 21, 23 15 16 17, 18 38 37 36 35
26 28 30
SCL D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 +5 V SDA
SWC RSTW WE
47 24 32 51 52 53 54 55 56 57 58 59 60 61 62
45 44 43 42 41 40 39
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 YOUT UOUT VOUT SDA SCL HDFL VDFL
SAA4956TJ
34 33 32 31 30 29 28 27 24 RE
SAA4977H
38 37 36 35 34 79 76 74 1 2
63
20 22 HRD 71 14 to 16, 21, 27, 31, 72 48 to 50, 3 to 7, 68 33, 65, 73, 10, 12, 70 77, 78 13, 64, 66 n.c.
VA HA
DISPLAY PLL
SRC
MBK914
Fig.20 Application diagram.
1998 Dec 08
29
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
12 PACKAGE OUTLINE SOJ40: plastic small outline package; 40 leads (J-bent); body width 10.16 mm
SAA4956TJ
SOT449-1
X D c
y
eE
bp
b1 40 21 A wM
E
HE A
A2
pin 1 index A1 (A 3) 1 e ZD vM A detail X 20 Lp
0
5 scale
10 mm
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT mm A max. 3.68 A1 1.40 1.14 A2 2.29 2.18 A3 0.25 bp 0.51 0.38 b1 0.81 0.66 c 0.32 0.18 D(1) 26.2 25.9 E(1) 10.3 10.0 e 1.27 eE 9.4 HE 11.30 11.05 Lp 1.4 1.1 v 0.18 w 0.18 y 0.1 ZD
(1)
1.19 0.73
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT449-1 REFERENCES IEC JEDEC MS027 EIAJ EUROPEAN PROJECTION
ISSUE DATE 97-06-02
1998 Dec 08
30
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
13 SOLDERING 13.1 Introduction to soldering surface mount packages
SAA4956TJ
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 13.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. 13.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1998 Dec 08
31
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
13.5 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP HLQFP, HSQFP, HSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not suitable(2) suitable not recommended(3)(4) not recommended(5) suitable suitable suitable suitable suitable
SAA4956TJ
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1998 Dec 08
32
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
14 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA4956TJ
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 15 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 16 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1998 Dec 08
33
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
NOTES
SAA4956TJ
1998 Dec 08
34
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
NOTES
SAA4956TJ
1998 Dec 08
35
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 Internet: http://www.semiconductors.philips.com
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545104/00/01/pp36
Date of release: 1998 Dec 08
Document order number:
9397 750 04286

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